Flysig: Dataflow Oriented Delay-Insensitive Processor for Rapid Prototyping of Signal Processing

摘要

As the one-chip integration of HW-modules designed by different companiesbecomes more and more popular reliability of a HW-design and evaluation of thetiming behavior during the prototype stage are absolutely necessary. One way toguarantee reliability is the use of robust design styles, e.g.,delay-insensitivity. For early timing evaluation two aspects must beconsidered: a) The timing needs to be proportional to technology variations andb) the implemented architecture should be identical for prototype and target.The first can be met also by delay-insensitive implementation. The latter oneis the key point. A unified architecture is needed for prototyping as well asimplementation. Our new approach to rapid prototyping of signal processingtasks is based on a configurable, delay-insensitive implemented processorcalled Flysig. In essence, the Flysig processor can be understood as a complexFPGA where the CLBs are substituted by bit-serial operators. In this paper thegeneral concept is detailed and first experimental results are given fordemonstration of the main advantages: delay-insensitive design style, directcorrespondence between prototyping and target architecture, high performanceand reasonable shortening of the design cycle.